Description of Bo TPC and Electronics

Document #:

LARTPC-doc-235-v1

Document type:

Note

Submitted by:

Stephen Pordes

Updated by:

Stephen Pordes

Document Created:

07 Dec 2006, 20:32

Contents Revised:

24 Jan 2007, 13:18

Metadata Revised:

14 Apr 2008, 10:36

Abstract:

A description of Bo TPC and Electronics

Files in Document:

• 12-07-06 status (Bo_TPC_electronics_status_.pdf, 469.5 kB)
• Biasing proposal HJ 01-11-07 (electronics.ppt, 170.0 kB)
• Dan Edmunds description of system and ownership 4/19/07 (DE_Electronicslist.txt, 12.5 kB)
• Mechanical design for inner and outer shield boxes for BO electronics (Shield Cage for Bo Electronics.pdf, 872.6 kB)
• TPC 16 channel Readout Board (pmb_16) (TPC_pmb_16_card.jpg, 120.1 kB)
• TPC Bias Voltage Supply (TPCbiasvoltagesupply.jpg, 78.4 kB)
• Where to order a Bit-3 VME PCI Interface (FERMILAB_S.PORDES_1-1DOO8_042607.pdf, 63.0 kB)
• we propose the "wire number coordinate system" (Coordinate system proposal for LAr TPC.pdf, 292.4 kB)

Other Files:

• Bo status and description by H. Jostlen:1/16/07 (Bo_TPC_electronics_temp_1-16-07_.doc, 1.9 MB)
• Mechanical box design as of Feb. 2, 2007 (Bo TPC Electronics Shield Box Drawings.pdf, 1.4 MB)

Topics:

• Electrics and DAQ:Front End
• Electrics and DAQ:DAQ
• Systems:Bo
• Analysis:Pattern Recognition

Authors:

• Daniel Edmunds
• Hans Jostlein

Keywords:

Bo